1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more specifically, to an improvement of a semiconductor device comprising a power MOSFET and a method of manufacturing such a device.
2. Description of the Related Art
FIG. 21 is a diagram showing a cross section of a typical conventional power MOSFET. In this figure, reference numeral 81 denotes an n+-type Si substrate having a high impurity concentration, which serves as an n+-type drain layer. An n−-type epitaxial Si layer 82 having a low impurity concentration is formed on the n+-type Si substrate 81.
A p-type base layer 83 is formed selectively on a surface of the n−-type epitaxial Si layer 82, and further an n+-type source diffusion layer 84 having a high impurity concentration is formed selectively on a surface of the p-type base layer 83.
A gate electrode 86 is provided via a gate insulating film 85 on the p-type base layer 83 interposed between the n+-type source diffusion layer 84 and the n+-type epitaxial Si layer 82.
In a power MOSFET of the above-described type, that is, a planar type power MOSFET, a current path to the MOS device is taken from a rear surface of the n+-type Si layer 81 via the n−-type epitaxial Si layer 82. With this structure, the resistance during the device is on (ON resistance) depends on the thickness of the n−-type epitaxial Si layer 82.
Meanwhile, a depletion layer extends within the n−-type epitaxial Si layer 82, and therefore the maintenance of the withstand voltage is determined by the thickness of the epitaxial layer. Typical values of the ON resistance and withstand voltage are 1.52 (Ω) and 746 (V), respectively.
As described above, in the conventional power MOSFET shown in FIG. 21, the current path and the region where the withstand voltage is maintained are located at the same place. With this structure, if the thickness of the epitaxial layer is increased to raise the withstand voltage, the ON resistance is increased as well. On the other hand, if the thickness of the epitaxial layer is decreased to lower the ON resistance, the withstand voltage is decreased as well. Thus, there is a conflicting relationship between these points, and it had been difficult to satisfy these points at the same time.
Especially, in the case where a drain-source reverse directional withstand voltage should be maintained at 200V or higher, the resistance of the n−-type epitaxial Si layer 82 needs to be increased. However, if the resistance REpi of the n−-type epitaxial Si layer 82 is increased, the lowering of the ON resistance is inevitably limited with the conventional structure. Note that the terms, resistance Rch and resistance RJFET indicate the channel resistance and junction FET resistance, respectively.
However, recently, a power MOSFET with a new structure called super junction structure, which can satisfy the above-described points at the same, has been proposed. FIG. 22 shows a cross section of a power MOSFET with the new structure. Note that the sections of this figure that correspond to those shown in FIG. 21 are designated by the same reference numerals and the detailed descriptions therefor will be omitted.
This power MOSFET is of a planar type; however, it has the following structure. That is, n-type epitaxial Si layers 87 (871 to 876) that have an impurity concentration higher than that of the n−-type epitaxial Si layer 82 are located at the center of the MOS, and p-type pillar layers 88 are located on both sides thereof. The p-type pillar layers 88 are formed to communicate to the p-type base layers 83, respectively. According to this structure, the current path and the region where the withstand voltage is maintained are separated from each other.
With this structure, the main current flows through the n-type epitaxial Si layer 87, and therefore the ON resistance depends on the impurity concentration of the n-type epitaxial Si layer 87. On the other  hand, the maintenance of the withstand voltage, since the depletion layer is extended in a lateral direction, is determined by the impurity concentration and width of each of the n-type epitaxial Si layer 87 and the p-type pillar layers 88. Thus, it is possible to satisfy both of the decrease in the ON resistance and the increase in the withstand voltage. Note that in the case of, for example, the 600V class, the ON resistance can be decreased to ⅓ or less of that of the planar type element shown in FIG. 21.
However, the power MOSFET with the conventional super junction structure entails the following drawbacks.
That is, in order to form the new structure shown in FIG. 22, a series of steps that include growing a thin n-type epitaxial Si layer 82, ion implantation of arsenic (As) as an n-type impurity, forming of a mask 90 for implantation of a p-type impurity, and ion implantation of boron (B) as a p-type impurity, must be repeated.
Specifically, in the case of a 600V-class element, the thickness of the n-type epitaxial Si layer 87 is about 50 μm whereas the thickness of the n-type epitaxial Si layer 82 is about 8.3 μm. Therefore, the above-described series of steps must be repeated 5 or 6 times.
In this case, 5 or 6 times of the epitaxial growth step, 10 or 12 times of the mask formation step and 10 or 12 times of the ion implantation step are required. After that, annealing is carried out to activate the n-type and p-type impurities that have been ion-implanted, and thus the n-type epitaxial Si layer 87 and the p-type pillar layers 88 are completed.
As described above, the manufacture of the power MOSFET having the conventional super junction structure requires a significantly greater number of processing steps as compared to the case of the planar type power MOSFET. Thus, the production cost is increased. More specifically, the production cost for the chip of the conventional power MOSFET would be almost the same as that of the planar-type large-area chip (of a low ON resistance type).
Further, in order to form a p-type pillar layer 88 such as to connect the p-type layers located above and below (, which are layers formed by ion implantation of B shown in FIG. 23D), it is necessary that B ions that are implanted should be diffused in a vertical direction (thickness direction) by at least the thickness of the n−-type epitaxial Si layer 82.
During this process, B ions diffuse in a lateral direction. Therefore, there is a drawback in which the reduction in measurement of the element in the lateral direction of the unit cell (measurement in its channel length direction) is hindered by the diffusion of B in the lateral direction.
Specifically, in the case of an element of the 600V class, the thickness of the n-type epitaxial Si layer 87 is about 5 to 8 μm. Therefore, taking the diffusion in the lateral direction into consideration, the width of the unit cell of the element would be about 30 μm.
FIG. 24 shows a termination structure used in the power MOSFET having the conventional super junction structure. In this figure, reference numeral 91 denotes the source electrode and numeral 92 denotes an insulating film.
The termination structure is formed of repetitions of the n-type epitaxial Si layer 87 and the p-type pillar layers 88. In order to relax the electrical field within the n−-type epitaxial Si layer 82, it is necessary to increase the potential gradually from the source to drain.
Specifically, in the case of an element of the 600V class and the width of a unit cell is about 30 μm, 10 to 20 unit cells are required in terms of the unit number. Therefore, a termination structure having a length of 300 μm to 600 μm is required. Such a long termination structure hinders the reduction in measurements of the entire device.
As described above, the power MOSFET with the conventional super junction structure is different from the planar type power MOSFET in that the lowering of the ON resistance and the increase in the withstand voltage can be achieved at the same time. However, the power MOSFET with the conventional super junction structure entails the problem of involving a far greater number of processing steps in the manufacture thereof as compared to that of the planar type power MOSFET.